Delta Sigma (DS) Analogue to Digital Converters (ADCs) and Digital to Analogue Converters (DACs) have become very popular converters for high-resolution applications because of their oversampling and noise shaping nature. These characteristics make them more robust to their components' nonlinearities and nonidealities. Indeed, by trading accuracy with speed, DS converters have become more attractive in the context of present CMOS technology evolution.
DS converters can be realized in either Switched-Capacitor (SC) or Continuous-Time (CT) approach. Nowadays, SC modulators (converters) are widely used in commercial applications as they can be more efficiently realized in the standard CMOS technology and provide a highly controllable design as well as being highly insensitive to clock jitter problems. Indeed, SC modulators are theoretically well understood and studied. However, SC realizations suffer from some problems. One of the biggest drawbacks of them is their relatively high power-consumption which arises from their nature, namely that of a switching capacitor. The other main problem of SC DS converters is their relatively low-speed nature arising from the fact that the required bandwidth for their op-amps is at least more than five times bigger than the sampling frequency. Also, a SC converter needs an anti-aliasing filter at the input of the modulator to prevent aliasing.
Referring to FIG. 1, a general scheme of a CT DS modulator (converter) is shown comprising a loop-filter 111, an n-bit ADC 112 (also called an n-bit quantizer) and an n-bit DAC 113. ADC 112 and DAC 113 are clocked; the sampling operation of the converter is performed at the input to ADC 112. In contrast to SC DS converters, CT DS converters perform the sampling operation inside the modulator-loop and so shape the sampling error to be out of the bound of interest. Hence, the bandwidth requirements of the op-amps in the converter are reduced. Moreover, as there is no switching inside the loop-filter, the power consumption of the op-amps and the integrators are substantially decreased. These characteristics make CT DS converters more suitable for high-speed applications. CT DS converters are described for example in Schreier, and B. Zhang, “Delta-Sigma Modulators employing Continuous-Time Circuitry,” IEEE Transaction on Circuits and Systems—I, Vol. 43, No. 4, pp. 324-332, April 1996; O. Shoaei, and M. Snelgrove, “Optimal (bandpass) Continuous-Time Sigma-Delta Modulator,” IEEE International Symposium on Circuits and Systems, Vol. 5, pp. 489-492, June 1994; and Robert H. M. van Veldhoven, “A Triple-Mode Continuous-Time Sigma-Delta Modulator With Switched-Capacitor Feedback DAC for a GSM-EDGE/CDMA200/UMTS Receiver,” IEEE Journal of Solid-State Circuits, Vol. 38, No. 12, pp. 2069-2076, December 2003.
Besides the advantages of CT circuitry with respect to their higher bandwidth and/or lower power-dissipation, there are some limitations in achieving high Signal-to-Noise-plus-Distortion ratio (SNDR) from them. The asymmetry of falling and rising edges of the feedback signal, sensitivity to feedback-delay and susceptibility to clock jitter are the biggest obstacles in designing CT DS modulators. Yet, the first two problems have been studied well and some robust techniques and solutions have been proposed to resolve them.
Clock-jitter predominantly affects SC DS modulators only at the sampling time of the input signal and hence because of the oversampling nature of the modulator its effect is attenuated in the band of interest at the modulator's output by the factor of the OverSampling Ratio (OSR). However, in CT DS modulators, clock jitter changes the feedback value by altering the signal pulse-width of the feedback coming to the loop-filter. Approximately, clock jitter in CT DS modulators has in the order of the square of the OSR worse effect than in SC DS modulators and is a severe problem in designing CT DS modulators.
This problem has been addressed in EP-A-1147609, which is described below with reference to FIGS. 2 and 3. In EP-A-1147609, the DAC 113 of FIG. 1 is replaced by a capacitor that is charged to different reference voltages, depending on the value of the digital signal, and then discharged through a passive or active resistor. Nevertheless further improvements are desirable, particularly in reducing power consumption.
WO2004/034588 discloses circuits for reducing clock jitter in a CT DS modulator, wherein, for digital to analog conversion, a control voltage is generated by discharging capacitor until the voltage on the capacitor reaches a level determined by a comparator. Problems with this arrangement include excessive power requirements, caused by the waveform of the capacitor, and clock jitter and circuit complexity caused by use of a comparator.
Class D Amplifiers are also very susceptible to clock jitter (and also power supply variations) because they involve large signal transitions. This is similar to the problem of the feedback DAC in CT DS converters. Suppressing clock jitter is therefore also desired in class D amplifiers to maintain accuracy. Class D amplifiers frequently have the load coupled in an H-bridge configuration, where the load output is switched between two reference voltage levels. H-bridges are widely used in hearing-aid devices because of their low-power, low-voltage compatibility. Using one battery cell, the output of the amplifier is switched between the ground and power supply rails. Clock jitter causes an additional noise floor on the output signal as it changes the duration of on and off switches. Also, switching the output load causes variations on the two rails and therefore decreases the dynamic range and precision of the amplifier.
Therefore, a need exists to have improved techniques for suppressing clock-jitter in CT DS modulators and also in class D amplifiers.